It's the end of the world as we know it! Xilinx and Altera working
My sleep deprivation is getting deeper, after multiple incidents of overtime at work. Usually, at this time of the week, I have recovered from the heavy days and early mornings of Monday and Tuesday. But even half asleep, it seems that the field programmable module of my brain is keenly at work.
Last Saturday, a discussion over FPGA mining triggered the idea of building a mining cluster. In fact, the idea of distributing the work over several miners had been on my mind for some time, but only in the context of area-optimizing a single chip. I realized I could adapt my good old serial-port code for the interconnects, so the miners could be more independent. By Sunday evening I had it working on a single chip, and on Monday an unholy alliance between Xilinx and Altera was up and running. I have since developed smaller improvements that also help with my standalone miner — which is now just a special case of a cluster node.
I guess the thought of clustering had not crossed my mind due to a lack of hardware; in fact, combining my two very different boards is rather inefficient compared to running them separately. Nevertheless, the code feels like a huge accomplishment, especially seeing how far my earlier choice of a serial port can go. I have basically written the equivalent of a USB hub for RS232, since you can use a single miner directly, or combine them with a hub. Or daisy chain the hubs for bigger clusters.
While my initial FPGA miner did get some positive attention, things are looking seriously big this time. It looks like I'm in for some tangible rewards ;) There is also the strange feeling of kudos when people way more professional in the field take interest in your work :-j