2011

Tue, Jun 28

<17:41 EEST> This week's geek news covers a couple of silencing enhancements. Two weeks ago I got a fanless PSU to replace the somewhat noisy and glitchy basic model in nanite. To my best knowledge, Seasonic X-Fanless is the most powerful fanless PSU out there, at least within a hobbyist price range. It says something about build quality when a 460-watt model can easily outdo a 620-watt one; of course, there are different ways of reporting the nominal power, be it input or output, peak or continuous. Nevertheless, that machine got a little quieter, but then there was another little problem.

As often happens with silencing mods, the next noisiest component then became apparent. In this case it was the stock CPU fan of the Kontron motherboard. Yet another one of these silly low designs, where the fan is trying to push air through the CPU. Anyone with an idea of fluid mechanics knows that it does not quite work, and you need to crank up the RPM.

This case was complicated by a pocket of hot air surrounding the motherboard, mostly due to the GPUs. I did find a nice big heatsink to replace the whiner, but it was still quite hot, and it is hard to place another (quieter) fan anywhere near. The simple solution was to cut back any persistent CPU usage, such as GIMPS, as I had just finished testing a prime candidate. Now the only fans are the big and slow GPU coolers, and the noisiest computer around is by far this laptop.

Finally, I could try and enjoy some classical music. Or interpretations thereof, as I have just discovered Retuperän WBK. I had actually heard them live once, during the Wappu at Dipoli in 1998, but this time I was intrigued by a recent review. It turns out that my impression of silly technology students playing the wrong notes was severely off the key; these are seriously talented musicians with ingenious arrangements. To summarize, they are the bastard pop of classical music.

Mon, Jun 13

<20:41 EEST> What happens when a script's output is directed into /dev/null, but you have no device nodes? The obvious answer is that the output is written into a regular file with that name. Then you have a nice piece of evicende that it was due to udev (Gentoo release 171-r1, to be specific) why my ARM server did not boot after a recent crash.

On a less geeky note, last Saturday was an important milestone for my band Serious Dudes, as we played a semi-professional gig at a huge birthday party. While it had been our aim for most of the spring, it was only the past week that we could train more intensely, almost every day. It felt like a moderate success, and instead of a thorough summer holiday, we are already looking at new rehearsals in a few days to keep up the routine for similar future gigs.

Soon after the gig, me and our resident guitar shredder went to town with a couple of his friends. It was a great opportunity for me to meet up with some new people, and I ended up making genuine friends. Not something that usually happens to me on a bar night.

Finally, it seems that my FPGA Bitcoin miner has gained some attention, and I find myself being treated like any other serious FPGA developer :-j

Wed, Jun 8

<13:13 EEST> It was a summer's tale: just a boy, his FPGA, and a head full of dreams.

The interleaved geeking out between music and hardware programming reached a balance just two weeks after the Linux song. Saturday the 4th was a national end-of-school day, and besides sending my precious students off into the real world, I managed to do the same to a Bitcoin FPGA project.

For a while, I had been trying to get a SHA-256 module to run on my Nexys 2, since some people were already mining on their FPGAs. Then an open source implementation was released. Unfortunately, it was tied to Altera systems in a couple of ways, including communication via 'virtual wires' over JTAG. I had already been playing with serial port communications for a lot of my toy FPGA projects, so it was the obvious replacement to try. The remaining bit of replacing an Altera PLL with a Xilinx DCM was quite straightforward.

The most frustrating part was probably on the computer's side, getting just the right format for input and output data. Already last autumn I had started to implement a toy miner in Python, both to be able to mine on a big-endian machine, and to understand the entire process. I never quite finished that, and later Pyminer was released, but I am still confused with all these endian issues. It would be simple if we only had to reverse the order of bytes, for example, but depending on the kind of data, it could also be two-byte or 4-byte words. As a result, Pyminer does not work on big-endian machines :-/

One thing that attracts me about FPGAs is that you are back to dealing with raw bitwise numbers in their natural order, and none of this shit with the historical accident of x86 processors. Incidentally, converting data between Bitcoin getwork and the FPGA code only requires a simple bytewise reverse. Even this has a few caveats for a newbie like me, since the network data is hexadecimal written as a string, and one byte is two hex digits. In the meantime, your FPGA code can also have bugs, and it is sometimes hard to pinpoint a problem. I am now quite used to debugging raw bytes with 7-segment displays, in fact, I think it is a terrible waste to use 4 of them to display 0000 to 9999, when you can go up to 2³² with raw bytes :-j

Anyway, the code is now in a working order, though there are some improvements under planning. Yesterday I rewrote the mining script in a threaded fashion, both to reduce errors in some corner cases, and to facilitate some fancy features in the future. While I have written threaded Python before, it was a simple case of independent daemons, and this time I needed some communication between the threads. The Event and Queue classes were the answer. It was quite a day with temperatures nearing 30°C and band rehearsals for an intermission.

At this point, I am itching to get a much more powerful FPGA, as this toy only manages about 3 Mhash/s, though with an impressive power efficiency. Unfortunately, people are reporting issues with stronger Xilinx series, such as Spartan 6 and Virtex 5. I also do not like the fact that you need to buy a license to program some of the stronger chips, as if you did not already pay for the actual hardware. I am starting to understand why the original developer went with Altera, though I have yet to see how well they play with Linux.